uLektz Skills

Learning Path

Non-Linear: Random Order

About the Course

Course Description

This course provides students with concepts of Review of number systems and Binary codes, Error detection and correction codes (Parity and Hamming code), Digital Logic Families, Combinational logic, Representation of logic functions and K-map representations

Objectives

1.Will familiarize about Multiplexers and demultiplexers

2.Will demonstrate Level triggering and edge triggering

3.Will develop Asynchronous and synchronous type

Prerequisite

There is no particular prerequisite to learn Digital Logic Circuits you will be able to do very well, if you have these basic skills:

1. Good Analytics Skills

2. Good Understanding Skills

3. Good Communication Skills

Course Study Materials

Module 1: NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES

1.1 Review of number systems and Binary codes
1.2 Error detection and correction codes (Parity and Hamming code)
1.3 Digital Logic Families
1.4 Operation
NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES - ASSESSMENT 10 Questions

Module 2: COMBINATIONAL CIRCUITS

2.1 Combinational logic
2.2 Representation of logic functions
2.3 K-map representations
2.4 Minimization using K maps
2.5 Multiplexers and demultiplexers
2.6 Code converters
2.7 Adders
2.8 Subtractors
COMBINATIONAL CIRCUITS - ASSESSMENT 10 Questions

Module 3: SYNCHRONOUS SEQUENTIAL CIRCUITS

3.1 Sequential logic
3.2 Level triggering and edge triggering
3.3 Asynchronous and synchronous type
3.4 Shift Registers
3.5 Moore and Melay models
3.6 Counters
3.7 State diagram
3.8 State reduction
SYNCHRONOUS SEQUENTIAL CIRCUITS - ASSESSMENT 10 Questions

Module 4: ASYNCHRONOUS SEQUENTIAL CIRCUITS AND PROGRAMMABLE LOGIC DEVICES

4.1 Asynchronous sequential logic circuits
4.2 Transition table
4.3 Flow table
4.4 Race conditions
4.5 Analysis of asynchronous sequential logic circuits
4.6 Introduction to Programmable Logic Devices: PROM – PLA –PAL
ASYNCHRONOUS SEQUENTIAL CIRCUITS AND PROGRAMMABLE LOGIC DEVICES - ASSESSMENT 10 Questions

Module 5: VHDL

5.1 RTL Design
5.2 Combinational logic
5.3 Sequential circuit
5.4 Operators
5.5 Subprograms
VHDL - ASSESSMENT 10 Questions

FINAL ASSESSMENT

FINAL ASSESSMENT 20 Questions

The certificate issued for the Course will have

Student's Name
Photograph
Course Title
Certificate Number
Date of Course Completion
Name(s) and Logo(s) of the Certifying Bodies

Only the e-certificate will be made available. No Hard copies. The certificates issued by Sharnbasva University, Kalaburagi . can be e-verifiable at www.ulektzskills.com/verify.

Students will be assessed both at the end of each module and at the end of the Course.
Students scoring a minimum of 50% in the assessments are considered for Certifications